A Shared Platform to Build Edge AI Semiconductor Products in Viet Nam
Viet Edge AI should be presented as a shared development platform for Vietnamese institutions and companies that want to build practical Edge AI semiconductor products. The platform should connect algorithm development, AI models, accelerator/NPU architecture, SoC integration, FPGA prototyping, software, and eventual ASIC implementation. VNCHIP’s role is to provide a credible semiconductor engineering base and an open collaboration structure—not to imply that one company owns the national ecosystem.
Core message
- Designed for collaboration among universities, research centers, startups, product companies, and semiconductor engineering teams.
- From AI model → hardware architecture → FPGA prototype → software stack → product-oriented ASIC roadmap.
- Focus on efficient, practical inference at the edge: vision, robotics, cameras, industrial systems, smart infrastructure, and embedded AI.
Live demonstration: face detection and recognition
The live demo should use a camera feeding an FPGA system that runs a VNCHIP-developed NPU or NPU subsystem. The system detects faces in a live video stream and, where permitted and appropriately consented, demonstrates recognition against a small local demo database. The purpose is not the application itself; the application is a visible proof that VNCHIP can integrate AI compute, memory movement, control software, camera/video data paths, and system-level FPGA implementation. The setup includes the following:
- FPGA board with the camera attached to it. We should have a stand so the camera can be firmly face the front of the booth.
- A desktop monitor with HDMI interface: live camera image with bounding boxes and inference status.
- A control laptop: hardware telemetry through microUSB cable, can change parameters, enroll a new face.
- Demo is working in “privacy mode” mode that performs face detection only and does not store faces. Recognition should be limited to pre-enrolled demo participants or staff with consent.
What the organizer must prepare
- One stable demo counter with camera mount, FPGA board, power supplies, cooling clearance, and cable management.
- One 27–32 inch monitor facing the aisle; a second smaller engineering monitor is optional.
- Controlled front lighting so detection remains stable throughout the day.
- A physical “demo boundary” mark so visitors know where to stand for camera interaction.
- A backup recorded demo video on the presentation PC in case of camera, FPGA, or software failure.
Partnership call-to-action
The local team should prominently display a partner invitation:
“Bring your model, sensor, IP, software, or application. Let us build and benchmark the Edge AI platform together.”
Use QR codes for separate partner categories: Research / University, Product Company, Semiconductor / IP, and Investment / Strategic Partnership.
