Demonstrating world-class physical design and deep sub-micron implementation proficiency, VNCHIP has successfully completed hierarchical Auto Place & Route (APR) and sign-off verification on TSMC's advanced N3E (3nm EUV) process node for an AXMM top-block customer design.
Key Highlights:
- Block Size: ~2.5 x 2.5 mm
- Partitions: 4 hierarchical sub-blocks
- Frequency: 800 MHz target operating speed
- Instance Count: 11 Million instances
- Signoff Sign-off: Timing closure (STA), DRC / LVS / ANT / ERC / PERC, Full EM/IR sign-off, Full IP checklist
The project encompassed complex multi-corner multi-mode (MCMM) timing closure, dynamic voltage drop IR analysis, signal integrity signoff, and physical verification to ensure first-pass silicon success.
